A Laterally Diffused Metal Oxide Semiconductor (LDMOS) is widely applied in the fields of a cellular phone base station, television and radio, radar, etc. A radio frequency characteristic of the LDMOS requires the resistance of its gate to be as low as possible in contrast to other types of Metal-Oxide-Semiconductor (MOS) field effect transistors. In order to lower the resistance of the gate, a process for lowering the resistance is performed on the gate, that is, a metal silicide is formed on the gate to lower the resistance of the gate.
In the prior art, the low-resistance gate satisfying the LDMOS requirement is typically manufactured in the following process.
The first step is to deposit a polycrystalline silicon layer on a semiconductor substrate.
The second step is to etch the polycrystalline silicon layer to form a gate body.
The third step is to define a body region and a drift region and to perform source/drain region implant and P+ implant.
Referring to FIG. 1A, the fourth step is to deposit a thick oxide layer 12 on the top of the gate body 11 and the semiconductor substrate 10 to form a structure as illustrated in FIG. 1A.
Referring to FIG. 1B, the fifth step is to polish the thick oxide layer 12 through Chemical Mechanical Polishing (CMP) until the top of the gate body 11 to form a structure as illustrated in FIG. 1B.
Referring to FIG. 1C, the sixth step is to form a titanium-silicon compound layer 13 on the top of the gate body 11 to form a structure as illustrated in FIG. 1C.
The seventh step is to remove the thick oxide layer 12 through dry etching.
In the foregoing fifth step, polishing the thick oxide layer until the gate body in practice may inevitably damage polycrystalline silicon constituting the gate body and consequently change starting voltages of a polycrystalline silicon resistance and a chip, thus degrading the performance of the device.